
IDT7134SA/LA
High-Speed 4K x 8 Dual-Port Static SRAM
Military, Industrial and Commercial Temperature Ranges
Timing Waveform of Read Cycle No. 1, Either Side (1,2,4)
t RC
ADDRESS
t AA (5)
t OH
t OH
DATA OUT
PREVIOUS DATA VALID
DATA VALID
2720 drw 08
Timing Waveform of Read Cycle No. 2, Either Side (1,3)
t ACE
CE
OE
DATA OUT
t LZ (1)
t LZ (1)
t AOE (4)
t HZ (2)
t HZ (2)
VALID DATA (4)
I CC
t PU
t PD
CURRENT
I SB
50%
50%
2720 drw 09
NOTES:
1. Timing depends on which signal is asserted last, OE or CE .
2. Timing depends on which signal is de-asserted first, OE or CE .
3. R/ W = V IH .
4. Start of valid data depends on which timing becomes effective, t AOE , t ACE or t AA
5. t AA for RAM Address Access and t SAA for Semaphore Address Access.
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